![]() It also would only be PC compatible (and I believe cross platform compatibility is high on the PCI-SIGs priority list these days). Otherwise, some sort of broadcast system like you lay out would be needed but I think it would have to be limited to ports 80h and 81h. Maybe if an OEM wanted to dedicate a specific slot to a diag card, that could work on a modern system. IIRC we were able to set up enough memory space (I don’t recall if it was just address space, if it came from the CAR pool, or if we went against Intel’s recommendations and added another cache bank to the CAR pool) and hard code the IO ports we needed to get some basic text output.Īt least for the IO ports, something like that would be needed under the current spec. In our case, the BMC had the video hardware built into it and because it was integrated, we always knew what bridges it was behind and the amount of resources it would request. The BMC we used has Super IO capabilities and could receive data on port 80h, it still didn’t provide enough to satisfy customers either over a remove KVM or using the built in KVM redirection. When I was working for a server hardware company, there was a customer demand for video output ASAP because, even back in the Sandy Bridge days took forever and only got worse with multiple sockets. Intel) to write and debug code for which there is no obvious user. Two, it requires the system firmware writer (e.g. One, the endpoint configuration happens so late in the system bringup process that the POST codes are no longer that useful. These were not adopted, but instead the PCIe 3 spec (and later) allow the system firmware to detect a debug card type and if it feels like it, configure the system to route POST codes to go to that card.įrom what I can tell, there has been no adoption of this method for obvious reasons. ![]() I proposed two alternatives to achieve this:Įither assign a broadcast message to POST traffic, orĪllow specific I/O port ranges to be broadcast to all endpoints. This means that a port 80h I/O write will only go to a single recipient that’s been specifically configured for it.Ī truly transparent solution would be to mimic a broadcast capability on the PCIe bus. ![]() an endpoint must request I/O addresses and the firmware or operating system must assign them. On PCIe the entire topology must be configured for a write transaction to reach an endpoint. a port 80h write will be seen by all cards and as long as one card indicates that they are responsible for that region of memory, the topology will deliver the write to the card. The issue with PCIe vs PCI is that writes to I/O and regular memory are broadcast on PCI but on on PCIe. I’ll try to restate in case it doesn’t show up again.) (I don’t know what happened, but I wrote a long response and it vanished when I hit Post Comment. Posted in computer hacks Tagged bios, LPC, pc, post Post navigation We’re no strangers to PC hacks, here’s a committed hacker who after upgrading the RAM beyond that supported by the motherboard, was determined to make his machine boot windows, no matter how much it complained. After all, if it works, then there’s no need to change it. This all goes to prove that even though a modern PC may seem totally different from the first PCs from any viewpoint, there still are considerable vestigial remnants baked in there. demonstrates his faulty motherboard dumping POST codes encoding for a CPU error, giving at least somewhere to look to debug further. It turns out that POST codes can be accessed from this point with an appropriate POST card that can talk LPC. It also serves as the connection for the TPM feature, which usually appears as one of the motherboard connectors intended to be user-accessible. looked at a disassembly of the BIOS update image and saw a similar structure, with POST code data sent to port 0x80 just like machines of old.īut instead of an ISA CPU bus, we have the Low Pin Count (LPC) bus which is used to hook up the ‘super IO’ functions, controlling things such as fans, temp sensors, and other system management functions. ![]() See “out 0x80, al” in there? That’s a POST code being writtenĭo modern machines even run a POST test at all, or are there other standards? After firing up a Linux machine and dumping the first meg of memory address space, it clearly contained some of the BIOS code. You see, older ISA-based systems were much simpler, with diagnostic POST codes accessible by sniffing the bus with an appropriate card inserted, but the modern motherboard doesn’t even export the same bus anymore. One day, this machine refused to boot leaving some head-scratching to do, and remembering the motherboard diagnostics procedures of old, realized that wasn’t going to work for this modern board. Spends the day hacking Linux kernels, and to such an end needed a decent compilation machine to chew through the builds.
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